PrincipalManager Memory Design Engineer NRIs Return toINDIA

Responsibilities of your team willinclude but are not limited to: 1.Contributing to the development of new DRAM emerging memoryproducts and IPs by enabling the overall design layout andoptimization of Memory/Logic/Analog circuits 2.Supporting design validation & verification reticle experimentsand required tapeout revisions 3. Performingverification...

Responsibilities of your team willinclude but are not limited to: 1. Extensive knowledge of CustomCircuit Design Analog Design Verification and Layout 2. Familiarity with various memory design architectures 3. Knowledge about complete product design anddevelopment flow including: a. Memory Design b. Power network development & analysis c....

Responsibilities will include but are notlimited to: Contributing to thedevelopment of new product opportunities by assisting with theoverall design layout and optimization of Memory/Logic/Analogcircuits Parasitic modeling and assisting indesign validation reticle experiments and required tapeoutrevisions Overseeing and managing the layoutprocess...

Responsibilities will include but are notlimited to: Contributing to thedevelopment of new product opportunities by assisting with theoverall design layout and optimization of Memory/Logic/Analogcircuits Parasitic modeling and assisting indesign validation reticle experiments and required tapeoutrevisions Overseeing and managing the layoutprocess including...

Role andResponsibilities: Architect simulate and design accelerator architecture.You will interact with multifunctional engineering teams to findopportunities and requirements. Some of the job dutiesinclude: Implement performance functional andpower model for accelerator architecture exploration and functionalverification. Accelerators may include Analog AI...

Qualification: Bachelors or Masters in Electrical/ElectronicsEngineering with 618 years of proven experience Required courses covering electromagnetic transmission line and RFtheory analog design or similar fields of study orexperience. Strong SI/PI/EMI theory andapplication modeling analysis simulation Signaland Power Integrity Background Experience...

Qualification : Bachelors or Masters in Electrical/ElectronicsEngineering with 618 years of proven experience Required courses covering electromagnetic transmission line and RFtheory analog design or similar fields of study orexperience. Strong SI/PI/EMI theory andapplication modeling analysis simulation Signaland Power Integrity Background ...

Job Role: Validated handson experience with IP & SOC RTLdesign. Experience with microarchitectureAsynchronous digital designs & ASIC RTL integration.Strong fundamental knowledge of digital design Verilogsystem Verilog and scripting languages Deepknowledge of IP and SoC design flows and methodologies (Lint CDCSynthesis/STA Power) Excellent...

Job Role: Validated handson experience with IP & SOC RTLdesign. Experience with microarchitectureAsynchronous digital designs & ASIC RTL integration. Strong fundamental knowledge of digital design Verilogsystem Verilog and scripting languages Deepknowledge of IP and SoC design flows and methodologies (Lint CDCSynthesis/STA Power) Excellent...

Responsibilities: Build NAND product/Testchip test development validationcharacterization & qualification Partnerwith Process Integration yield engineering to improve overall dieyield and meet the critical milestones planned for thetestchip NAND product test mode definition andapplications Build Presilicon conceptualdesign and preparation work ...

Job Description Responsibilities will include but notlimited to: Drive and leadthe device technology development of stateoftheart CMOS providingsolutions that are compatible with the memoryarchitecture. Set up TCAD and waferexperiments to identify best solution for CMOSrequirements Align with Design on requiredperformance parameters Implement...

Job Description Responsibilities will include but notlimited to: Drive and leadthe device technology development of stateoftheart CMOS providingsolutions that are compatible with the memoryarchitecture. Set up TCAD and waferexperiments to identify best solution for CMOSrequirements Align with Design on requiredperformance parameters Implement...

JobResponsibilities ConductESD/LUP research and experiments to investigate how to designin thebest ESD and latchup design and layout solutions that minimizeproduct defects due to electrostatic discharge (ESD) or latchup(LUP) events. Design ESD test structures tofully evaluate the high current and voltage properties of the ESDIO input or power clamps...

Be the Product Development TeamLead guiding a multifunctional product development engineering teamto deliver SSD products aligned with a product delivery roadmap andschedule. Act as the Technical authority inthe program guiding the Engineering teams and providing updates ondevelopment progress and technical issue resolution to the uppermanagement. Be the...

Skills Required : 1020 yearsof proven experience in Synthesis/STA Goodunderstanding of overall design Flow RTL to GDS. Experience in signing off the full chip synthesis/STA fortapeouts Handson Experience in constraintgeneration and management for hierarchical designs. Detailed Understanding of DFT Constraints. Handon Synthesis & STA Experience on Lower...

Skills Required: 1020 yearsof proven experience in Synthesis/STA Goodunderstanding of overall design Flow RTL to GDS.Experience in signing off the full chip synthesis/STA fortapeouts Handson Experience in constraintgeneration and management for hierarchical designs.Detailed Understanding of DFT Constraints.Handon Synthesis & STA Experience on Lower...

Responsibilities: Architect andlead other architects working on DC & Auto SSDfeatures Innovate solve DC challenges in areasof power performance endurance & overall value add.Work with global architects to align architectureglobally Work with India architect design anddevelopment to align locally Work with DC& Auto business and system architect to align on...

Job Responsibilities: Minimum of 8 years of handson physicaldesign implementation experience along with APR flow developmentand PPA analysis STA closure atblock Experience in Advanced processtechnology nodes (6/7 nm preferred) Experiencewith Cadence layout tools (Innovus Tempusetc..) Handson work experience in Physicalverification closure (DRC/LVS/Antenna)...

Job Responsibilities: Minimum of 8 years of handson physicaldesign implementation experience along with APR flow developmentand PPA analysis STA closure atblock Experience in Advanced processtechnology nodes (6/7 nm preferred) Experiencewith Cadence layout tools (Innovus Tempus etc..) Handson work experience in Physicalverification closure...

Preparation and filing of individualreturns of NRIs and expatriates (inbound and outbound) MaintainingTax return tracker Preparation of Missing information details fortax return preparation Interacting with client serviceteams/overseas Deloitte offices Preparation of challans downloadingand reconciliation of Form 26AS/Annual Information StatementDownloading...