ASIC STA Engineer NRIs Return to INDIA

1 month ago


Sany, India GLOBALTALEX PRIVATE LIMITED Full time

Skills Required:

    • 1020 yearsof proven experience in Synthesis/STA
    • Goodunderstanding of overall design Flow RTL to GDS.
    • Experience in signing off the full chip synthesis/STA fortapeouts
    • Handson Experience in constraintgeneration and management for hierarchical designs.
    • Detailed Understanding of DFT Constraints.
    • Handon Synthesis & STA Experience on Lower NodeTechnologies with Synopsys/Cadence Tools.
    • Handson Experience on Equivalent Checks with Synopsys /Cadence Tools.
    • Good knowledge of TimingBudgets.
    • Knowledge of Perl / TCL / Pythonscripting language
    • Experience in multivoltagedesigns using CPF/UPF.
    • Good understanding ofthe Chip Interface Constraint Generation & TimingClosure.
    • Handson experience in power analysisusing PTPX
    • Good understanding of VHDL /Verilog Constructs.

Responsibilities:

    • Responsible for Block/ Chip TileSynthesis to achieve the best PPA.
    • ConstraintGeneration & Maintenance for Block / SOC for sophisticatedhierarchical Designs for all the Modes.
    • Interaction with Design DFT IP&PD teams for TimingConvergence & Resolving Constraint Conflicts.
    • Able to work on lowpower & verify lowpower intentwith minimal direction.
    • Responsible forLogical equivalence checks & Low Power Checks.
    • Early RTL analysis for Clocking Power DFT coverage &suggestions to the Designer on the improvements.
    • Support Verification team to enable GLS.


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