Design verification Engineer
3 weeks ago
: RTLDesign VerificationEngineer
:5 Years
:Bangalore/Bhubaneswar
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- Developand execute verification plans for complex RTLdesigns.
- Perform functional and performanceverification of design blocks.
- Collaborate withcrossfunctional teams to ensure successful IP componentintegration.
- Contribute to enhancingverification methodologies and bestpractices.
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Bachelorsor masters degree in electrical engineering/Electronics &Communication Engineering or relatedfield.
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Minimumof 5 years of experience in RTL designverification.Proficiency in Verilog/ SystemVerilog and experience with industrystandard verificationmethodologies (OVM/UVM).Strong understandingof ASIC design flow and verificationtechniques.Excellent problemsolving anddebuggingskills.
:
- Experiencewith formal verification tools andmethodologies.
- Familiarity with scriptinglanguages (e.g. Python Perl) for automationtasks.
- Knowledge of industrystandard protocolsand interfaces (e.g. PCIe AXIAHB).
:
- Opportunitiesfor professional growth and careeradvancement.
- Vibrant and inclusive work culturethat values collaboration andinnovation.
If youreready to take your career to the next level and contribute togroundbreaking projects we want to hear fromyou
/
: Pleasename the file in the following format: YourFull
.
design,verilog,rtldesign,communication,universal verification methodology(uvm),semiconductor device
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