RTL Design Verification Engineer

3 weeks ago


sany, India ARF Full time
: /
L ocation: Bangalore/Ranchi/BhubaneswarnoticePeriod: ImmediateJoiner Experience : 612 YearsExperience
Wereseeking a skilled Sr RTL Verification Lead to join our team. As anIP Verification Engineer youll be part of a highly motivated teamresponsible for DV for IPs like UCIe HBM PCIe Bus logicetc.
: BE/ME/MTech/MSwith 6 to 12 years of RTL verificationexperience.Proficiency in advanced verification methodologies:UVM/OVM/VMM/System Verilog constrained random stimulus generationassertionbased verification and functional coveragetechniques.Familiarity with register verification standards and NLP/GLSverification flows.Experience in IP level and subsystem level verification onprotocols like PCIE UCIe HBM etc. is a strongplus. Relevantexperience in enabling and verifying controller interoperabilitytesting at the subsystem level isadvantageous.
Interestedor know someone who might be Drop me a message or send your resumeto

design,rtlverification,dv,ip,universal verification methodology(uvm),verilog,systemverilog



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