Physical Design Engineer

6 months ago


Hyderabad, India Microsoft Full time

Overview

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to develop new generation silicon is of paramount importance. To achieve this goal, Microsoft’s Cloud Compute Development Organization (CCDO) is seeking seasoned, passionate, driven and intellectually curious engineers to join our silicon hardware physical design team, covering RTL to GDS methodology, design convergence, and design quality for our projects. We are responsible for delivering cutting-edge, CPU-based custom SOC designs that can perform complex and high-performance functions in the most efficient manner. This team will be involved in numerous projects within Microsoft developing CPU based SOCs silicon for data centres.

Qualifications

BS/MS in Electronics or Electrical or Computer Engineering Min 5+ years of experience in semiconductor design. Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams. Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.

Preferred:

Large SoC/CPU/IP design tape-out experience in the latest foundry process nodes. Excellent project management skills and ability to juggle multiple projects at once. Strong understanding of constraints generation, STA, timing optimization, and timing closure. In-depth understanding of design tradeoffs for power, performance, and area. Hands on experience with CTS techniques such as Htree, custom clock tree, Experience of implementing (VA Planning, secondar PG planning) in multi-voltage, multi-powerdomain, and low power designs. Experience and knowledge of formal equivalency checks, LEC, LP, UPF, reliability, SI, and Noise. Experience in EDA tools such as Fusion Compiler, Primetime, StarRC, RedHawk, Formality, etc. Exposure and some hands-on experience with PD flows bring up/setup/flow flush, overall know how of PD-TFM and PD methodology is a big plus Strong problem-solving and data analysis skills Automation skills using scripting languages such as Perl, TCL, or Python.

Responsibilities

In this role, you will be responsible to: 

Own execution from synthesis to place and route of partition through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification. Own partition floorplanning for optimizing blocks for Power, Performance and Area. Additionally flow flush PD TFM on few design partitions for early identification of any design PD flow issues before every PD TFM release is proliferated and deployed across all partitions/subchips for PD execution. Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues upfront and ensure those are fixed in the next PD TFM release from CAD or are updated in the design project layer (as appropriate). Have close collaboration with RTL team to help drive and resolve design issues related to block closure. Understand tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach. Have good scripting skills in one or more scripting languages (viz., Tcl, Perl). Expertise in Python will be a big plus. Be a disciplined executor and have keen interest in learning and be forthcoming to deliver to requirements of the program, learn from senior team members. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.Industry leading healthcareEducational resourcesDiscounts on products and servicesSavings and investmentsMaternity and paternity leaveGenerous time awayGiving programsOpportunities to network and connect

  • Hyderabad, India Jones RecruitZo Full time

    Job Title: Senior ASIC Design Engineer (Physical Design & Timing Optimization) Location: WFO / Hyderabad) Experience: 5-8 Years Notice Period: 30- 45 days Job Description: We are looking for a skilled Senior ASIC Design Engineer with expertise in Physical Design and Timing Optimization . The ideal candidate will have hands-on experience with...


  • Hyderabad, India Jones RecruitZo Full time

    Job Title: Senior ASIC Design Engineer (Physical Design & Timing Optimization)Location: WFO / Hyderabad]Experience: 5-8 YearsNotice Period: 30- 45 daysJob Description:We are looking for a skilled Senior ASIC Design Engineer with expertise in Physical Design and Timing Optimization. The ideal candidate will have hands-on experience with Hierarchical and...


  • Hyderabad, India Jones RecruitZo Full time

    Job Title: Senior ASIC Design Engineer (Physical Design & Timing Optimization) Location: WFO / Hyderabad) Experience: 5-8 Years Notice Period: 30- 45 days Job Description: We are looking for a skilled Senior ASIC Design Engineer with expertise in Physical Design and Timing Optimization . The ideal candidate will have hands-on...


  • Hyderabad, Telangana, India Askexim Services (P) Limited Full time

    Job SummaryWe are seeking a highly skilled Physical Design Engineer to join our team at Askexim Services (P) Limited. As a Physical Design Engineer, you will be responsible for contributing to all phases of physical design of high-performance designs from RTL to delivery of our final GDSII.Key ResponsibilitiesGenerating block/chip level static timing...


  • Hyderabad, India Cyient Full time

    Title: Engineer/ Lead - Physical Design location: Bangalore / Hyderabad Exp : 6 to 20 yrs. Job Description In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...


  • Hyderabad, India Cyient Full time

    Title: Engineer/ Lead - Physical Design location: Bangalore / Hyderabad Exp : 6 to 20 yrs. Job Description In-depth knowledge and hands-on experience on Netlist2 GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...


  • hyderabad, India Cyient Full time

    Title: Engineer/ Lead - Physical Designlocation: Bangalore / HyderabadExp : 6 to 20 yrs.Job DescriptionIn-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design...


  • hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff Engineer Skills required: - Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n : In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...


  • hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff Engineer Skills required: Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n : In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...


  • Hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff Engineer Skills required: Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n : In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...


  • Hyderabad, India Coders Brain Technology Private Limited Full time

    Job Title : Physical Design (PD) EngineerExperience : 10-15 YearsLocation : Bangalore / HyderabadJob Description :Role Overview :We are seeking a highly experienced Physical Design (PD) Engineer with expertise in Cadence Innovus and lower node technologies (


  • Hyderabad, India Cyient Full time

    Physical Design Lead / Sr. Staff Engineer Skills required: Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n : In-depth knowledge and hands-on experience on Netlist2 GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...


  • Hyderabad, India Cyient Full time

    Title: Engineer/ Lead - Physical Designlocation: Bangalore / HyderabadExp : 6 to 20 yrs.Job DescriptionIn-depth knowledge and hands-on experience onNetlist2GDSIIImplementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing,STA,Power Integrity Analysis,Physical Verification,Chip finishing. Should have experience on Physical Design...


  • hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida ,Chennai and Ahmedabad Experience Required: 4+ ROLE & RESPONSIBILITIES - Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing...


  • hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida ,Chennai and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIES- Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...


  • Hyderabad, India EInfochips Full time

    Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida , Chennai and Ahmedabad Experience Required: 4+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing...


  • hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida ,Chennai and Ahmedabad Experience Required: 4+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...


  • hyderabad, India eInfochips (An Arrow Company) Full time

    Job Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida ,Chennai and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal...


  • Hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff Engineer Skills required: Job Title: Physical Design Lead (6 to 15 years ) Job Descriptio n :In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have...


  • hyderabad, India Cyient Full time

    Physical Design Lead / Sr.Staff EngineerSkills required: Job Title: Physical Design Lead (6 to 15 years) Job Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...