Senior Physical Design Engineer
2 days ago
Physical Design Lead / Sr.Staff Engineer
Skills required:
- Job Title: Physical Design Lead (6 to 15 years
)
Job Descriptio
n
:
In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and sub-micron technology of 16nm and lower technology nod
- es.
Must have hands-on experience on PnR Suite from Cadence & Synopsys (Innovus & - ICC2)Experience in Static Timing Analysis (PrimeTime - SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Cal
- ibre)Understanding the practical application of methodologies and Physical Design Tools, Flow Automation, and Improve
- mentsExperience in SOC integration, Low Power and High-Speed Design and Advanced Physical Verification Techn
- iquesExcellent Customer interaction, Communication, Teamwork skills and managing a team o
- f 10+Should have experience in handling >5M instance count, 1.5GHz frequency de
- signsShould have experience on programming in Tcl/Tk/Perl to automate design process and improve effic
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Senior Physical Design Engineer
6 days ago
hyderabad, India eInfochips (An Arrow Company) Full timeJob Role: Physical Design Engineer- Senior/Lead Location: Bangalore, Hyderabad, Noida and Ahmedabad Experience Required: 4+ ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity,...
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Senior Physical Design Engineer
2 weeks ago
Hyderabad, India eInfochips (An Arrow Company) Full timeJob Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...
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Senior Physical Design Engineer
3 weeks ago
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Senior Physical Design Engineer
3 weeks ago
Hyderabad, India eInfochips (An Arrow Company) Full timeJob Role: Physical Design Engineer- Senior/LeadLocation: Bangalore, Hyderabad, Noida and AhmedabadExperience Required: 4+ROLE & RESPONSIBILITIESEngineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power...
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Senior Physical Design Engineer
2 days ago
hyderabad, India Cyient Full timePhysical Design Lead / Sr.Staff EngineerSkills required: Job Title: Physical Design Lead (6 to 15 years) Job Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...
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1 day ago
Hyderabad, India Cyient Full timePhysical Design Lead / Sr.Staff EngineerSkills required: Job Title: Physical Design Lead (6 to 15 years) Job Description: In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on...
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3 weeks ago
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7 days ago
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3 weeks ago
Hyderabad, India MosChip® Full timeResponsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.Worked on 65nm or lower node...
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Senior Physical Design Engineer
3 weeks ago
Hyderabad, India MosChip® Full timeResponsibilities: Top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Worked on 65nm or lower node...
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