Senior Engineer, Physical Verification

6 months ago

Hyderabad, India Micron Full time

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

JR50860 Senior Engineer, Physical Verification

Required Experience :

5+ Years of relevant experience in the fields of IC design flow or PDK development for Memory/Mixed-Signal Design and Layout. Experience with LVS, DRC rule deck coding using Calibre SVRF. Experience in automation of IC design flows using Perl, Python, Bash, C-Shell coding. Familiarity with semiconductor electrical fundamentals and device physics. Capable of working in a cross functional and multi-site team environment spanning multiple time zones.

Additional desired Skills :

Experience in maintaining intranet portals such as confluence and SharePoint. Experience in SKILL coding. Knowledge of spice simulators such as HSPICE and Finesim. Hands on experience with schematic entry, netlist extraction, and post layout verification. Understanding of front/back end analog and mixed signal design flows and methodologies, problem solving skill.

Responsibilities will include, but are not limited to:

Code and maintain scribe design specific Calibre DRC/LVS rule decks. Implement automation scripts in Calibre SVRF, Perl, Python, Bash and C-shell. Develop and maintain automation solutions for scribe design specific Calibre DRC/LVS. Collaborate with Process Integration, CAD and PDK teams to mitigate physical verification rule deck issues. Advance and maintain test cases for evaluating PDK updates in IC design flow. Architect and coordinate development of validation methodologies for scribe design specific rule decks. Incorporate Data science and Machine learning to develop advanced verification solutions. Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits. Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions. Overseeing and managing the layout process including floor-planning, placement, and routing. Performing verification processes with modeling and simulation using industry standard simulators. Contributing to cross group communication to work towards standardization and group success. Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product. Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality. Driving innovation into the future Memory generations within a dynamic work environment

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