Design Verification Engineer
1 week ago
Role: Power Management/ Low power verification
Location: Bangalore, India, On-site role
Fulltime.
We just had an intake call, and we don't have a detailed job description.
Please see below
Power-aware verification with UPF annotated
Various power scenarios verification
Power vector generation for leakage, sleep, clock tree, and active use cases
Clock verification (Freq, spec compliance, Glitch analysis, Multiple cycle paths)
Reset verification (reset glitch analysis)
Power switch coverage analysis
Strong DV knowledge, SV, UVM-based test development
Power-aware verification - UPF-based RTL simulation
Power intent understanding
Power-aware GLS with PG netlist
Clock, reset architecture understanding for SoCs
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