Design Verification Engineer

2 days ago

Bengaluru, Karnataka, India Durapid Technologies Private Limited Full time

About The Role
We are seeking top-tier
Design
Verification Engineers
with proven expertise across the full verification cycle. The ideal candidate will be a
high-performing verification professional
with a deep understanding of SoC architecture, verification methodologies, and debugging techniques. You'll work closely with design and architecture teams to ensure first-time functional silicon success for large-scale SoCs.

Key Responsibilities

  • Drive end-to-end verification of complex SoC and IP blocks, from test planning to verification closure.
  • Develop verification environments using SystemVerilog/UVM or Specman/E.
  • Define and implement test strategies, test plans, and coverage-driven verification approaches.
  • Write, debug, and maintain SystemVerilog/UVM testbenches and constrained-random tests.
  • Collaborate with RTL and design engineers to identify, analyze, and debug functional issues.
  • Track and achieve coverage closure (functional and code coverage).
  • Contribute to verification infrastructure improvements and automation initiatives.
  • Participate in design reviews and help define verification methodologies and best practices.

Must-Have Skills

  • Strong hands-on experience in the complete chip verification cycle — from planning to closure.
  • Expertise in SystemVerilog/UVM or Specman/E for testbench development.
  • Deep understanding of SoC architectures, bus protocols (AMBA, AXI, AHB, APB), and memory subsystems.
  • Strong debugging skills for RTL and gate-level simulations using tools such as VCS, Incisive, or Questa.
  • Experience with constrained-random verification, coverage analysis, and assertion-based verification (ABV).
  • Proficiency in scripting (Python, Perl, or Tcl) for automation and regression management.

Skills: soc,systemverilog,vcs,debugging,specman,design

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