Senior/Lead Design Verification

2 days ago

Bengaluru, Karnataka, India SEMI LEAF Full time ₹ 20,00,000 - ₹ 40,00,000 per year

Job Title: Senior Design Verification Engineer – CPU & SoC Verification

  • Location: Bangalore /Hyderabad
  • Experience: 4– 10 Years
  • Job Type: Full-time
  • Education: B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, or Computer Engineering.

Job Summary:

We are seeking an experienced Senior Design Verification Engineer with strong expertise in CPU and SoC-level functional verification. The ideal candidate will be responsible for defining and executing verification strategies, developing advanced UVM environments, and ensuring functional correctness and robustness of CPU subsystems and SoC integrations.

Required Skills & Experience:

  • Proven expertise in SystemVerilog, UVM, and coverage-driven verification.
  • Strong experience in CPU/core-level verification (RISC-V, ARM, or custom processor).
  • Good understanding of CPU microarchitecture concepts — pipeline, branch prediction, MMU, cache coherence, interrupt, and exception handling.
  • Hands-on experience in SoC-level verification, including interconnect (AXI/AHB/APB), memory subsystem, and IP integration.
  • Proficiency with EDA tools (Synopsys VCS, Cadence Xcelium, or Mentor Questa).
  • Strong debug skills using waveform viewers (DVE, Verdi, SimVision).
  • Scripting skills in Python, Perl, or Shell for regression and automation.
  • Familiarity with emulation, FPGA validation, or formal verification is a plus.

Key Responsibilities:

  • Develop and own CPU core and SoC-level verification environments using SystemVerilog and UVM.
  • Define and drive test plans, coverage goals, and verification methodologies for CPU pipelines, memory hierarchy, cache coherence, and interconnects.
  • Verify integration of CPU subsystems, interconnect fabrics, memory controllers, and peripherals in the SoC.
  • Develop scoreboards, monitors, checkers, and assertions for functional verification.
  • Perform constrained-random, directed, and coverage-driven testing to achieve full verification closure.
  • Debug simulation failures, analyze waveforms, and work closely with RTL designers to resolve design issues.
  • Interface with architecture, design, firmware, and emulation teams to ensure complete functional validation.
  • Drive functional coverage closure and maintain metrics for verification completeness.
  • Contribute to automation and regression management, including scripting in Python/Perl/Tcl.
  • Mentor and guide junior engineers, review their test plans and verification environments.

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Job Type: Full-time

Pay: Up to ₹4,000,000.00 per year

Experience:

  • Design Verification : 4 years (Preferred)
  • SOC/CPU verification: 4 years (Preferred)
  • SystemVerilog: 4 years (Preferred)

Work Location: In person

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