Senior Design Verification Engineer

1 week ago

Bengaluru, Karnataka, India Thought Frameworks Full time ₹ 20,00,000 - ₹ 25,00,000 per year

Position :
Senior Design Verification (DV) Engineer

Experience :
5-9 years

Location :
Bangalore

Work Mode :
Work from office

Job Type :
Full-time

Job Summary
We are seeking a highly skilled and experienced Senior Design Verification (DV) Engineer with 5-9 years of experience to join our team in Bangalore. The ideal candidate will be a hands-on expert in SystemVerilog and UVM methodologies, responsible for implementing robust verification environments, analyzing test coverage, and debugging complex logic issues. This role is crucial for ensuring the functional correctness and quality of our chip designs through rigorous verification and testing.

Key Responsibilities

  • Verification Environment Development : Implement and debug advanced Design Verification (DV) environments and stimuli, utilizing industry-standard methodologies such as UVM.
  • Test Planning & Execution : Analyze coverage data and actively contribute to the development of comprehensive test plans to ensure thorough verification.
  • Test Case Development : Write and execute a variety of test cases, ranging from register-level and protocol-level tests to complex, real-world scenarios to validate design functionality.
  • Debugging & Issue Resolution : Investigate and debug complex logic issues identified during simulation. You will be responsible for performing root cause analysis and accurately filing bug reports for the design team.
  • Tool Proficiency : Utilize and be proficient with a range of simulation tools, including VCS, Specman, and other similar tools to run simulations and analyze results.
  • Collaboration : Work closely with design, architecture, and other verification teams to ensure all functional requirements are

fully verified and to drive a collaborative development Skills & Qualifications :

  • 5-9 years of relevant experience in Design Verification (DV).
  • Strong, hands-on skills in SystemVerilog and UVM (Universal Verification Methodology).
  • Proven experience in writing and debugging testbenches and test cases.
  • Familiarity with industry-standard simulation tools (VCS, Specman, etc.)
  • Excellent debugging, problem-solving, and analytical skills.
  • The ability to work on-site in Skills :
  • Experience with other verification methodologies or languages such as Specman/e or Python.
  • Knowledge of scripting languages like Perl or Python for automation.
  • Experience with formal verification and static analysis tools

)

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