
Memory Layout Engineer
2 weeks ago
Job Description for Memory Layout
Location: Bangalore
Experience 3yrs-10 Yrs
- Memory leaf cell layout development
- Migration of layout from one tech node to another
- Block and top level integration
- Quality and timely delivery
- EM-IR, area intensive layouts, Quality checks (QC)
- Understanding of design rules for 90nm and below
- Understanding of design rules for 14ff and 16ff is a plus.
- Drive multiple projects and provide necessary technical guidance to the engineers
- Understanding of DFM and DFY
- Understanding of memory compiler architectures
- Good debugging skills
- Knowledge of scripting in PERL/Shell/TCL scripting etc
- Proficient with tools like Cadence Virtuoso, Calibre LVS and Calibre DRC
- B.E. / B.Tech / M.E. / M.Tech
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