ASIC Physical Design, Sr Staff Engineer

We Are:
At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:
You are a passionate engineer who thrives in a collaborative and challenging environment. You have a strong desire to learn and explore emerging technologies, staying ahead in the rapidly evolving semiconductor landscape. Your analytical mindset and problem-solving skills enable you to tackle complex technical challenges creatively and independently. You possess deep expertise in ASIC physical design, particularly in implementing and optimizing high-speed DDR/HBM/UCIe/Die-to-Die IP at advanced technology nodes. You take pride in building efficient, high-performance silicon solutions and have experience with timing closure at frequencies above 2GHz, mixed signal integration, and clock tree synthesis with tight skew balancing. You are hands-on, detail-oriented, and able to technically lead and mentor a team of junior engineers, driving projects to successful completion with top quality and on schedule. Your effective communication skills allow you to work seamlessly with both local and global teams, including US counterparts, and you frequently engage with senior personnel across the organization. You are committed to continuous improvement and knowledge sharing, contributing to the growth of both your team and Synopsys as a whole. With at least 9 years of relevant experience, you excel at resolving issues, exercising independent judgment, and representing your team in company-wide initiatives. Your leadership inspires others, and you are always ready to guide peers and foster a culture of excellence and inclusion.

What You'll Be Doing:

• Lead the implementation and power signoff of world-class DDR/HBM/UCIe/Die-to-Die IP at cutting-edge technology nodes.
• Drive timing closure for high-speed designs (above :2GHz), ensuring robust performance and reliability.
• Integrate mixed signal and macro IP, optimizing for area, power, and performance.
• Design and balance clock trees with very tight skew requirements, overcoming complex technical challenges.
• Collaborate daily with local and US-based teams, providing technical expertise and updates on project status.
• Mentor and technically lead a team of 4-6 junior engineers, fostering skill development and project success.
• Utilize industry-standard tools such as DC, ICC2, PT-SI for physical design and signoff tasks.
• Represent Synopsys on business unit and company-wide projects, networking with senior internal and external stakeholders.

The Impact You Will Have:

• Deliver high-quality, high-performance DDR/HBM/UCIe/Die-to-Die IP solutions that enable next-generation silicon products.
• Enhance the efficiency and reliability of physical design flows at advanced process nodes.
• Accelerate project timelines through effective leadership and technical problem-solving.
• Drive innovation in clock tree synthesis and timing closure, setting industry benchmarks.
• Strengthen Synopsys' reputation as a leader in IP implementation and silicon design.
• Mentor and uplift junior engineers, contributing to the growth and success of the broader team.
• Facilitate seamless cross-functional and global collaboration, ensuring project alignment and delivery.
• Influence company-wide initiatives and represent the team in strategic discussions.

What You'll Need:

• Minimum of 9+ years of hands-on experience in ASIC physical design, preferably with DDR/HBM/UCIe/Die-to-Die IP.
• Strong proficiency with industry-standard EDA tools such as Design Compiler (DC), IC Compiler II (ICC2), and PrimeTime SI (PT-SI).
• Demonstrated expertise in timing closure at high frequencies (>2GHz) and clock tree synthesis with tight skew control.
• Experience in mixed signal and macro IP integration at advanced technology nodes.
• Proven ability to lead and mentor engineering teams, driving project execution and technical excellence.
• Prior knowledge in DDR power signoff and power optimization strategies is a plus.
• Excellent communication skills for technical interaction across global teams.

Who You Are:

• Innovative thinker with a proactive approach to problem-solving.
• Strong team player who values collaboration and inclusion.
• Effective communicator, able to articulate complex technical concepts clearly.
• Adaptable and resilient, thriving in fast-paced and dynamic environments.
• Mentor and leader, passionate about guiding and developing talent.
• Detail-oriented with a commitment to delivering high-quality results.

The Team You'll Be A Part Of:
You will join the SNPS DDR/HBM/UCIe/Die-to-Die IP implementation team, a diverse and forward-thinking group dedicated to designing and delivering cutting-edge silicon solutions. The team is known for its technical depth, collaborative spirit, and commitment to excellence. You will work alongside experts in physical design, verification, and IP integration, contributing to the development of industry-leading products and technologies.

Rewards and Benefits:
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.