Senior ASIC Physical Designer
6 days ago
Job Title: ASIC Engineer - Physical Design
With 2+ years of experience, you will be responsible for all aspects of Physical Design, including Floorplanning, Placement, Budgeting, Clock Tree planning and analysis, Scan re-ordering, and Routing.
Key Responsibilities:
- Expertise in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, and internal tools & flow is required.
- Collaborate with the methodology team to solve implementation challenges and provide inputs to improve the Physical design flow.
- Design automation experience and understanding of Timing constraints, SI prevention, and Power reduction are necessary.
- Familiarity with Synopsys/Cadence/Mentor place and route tools and prior experience with designs in 16nm and/or 7nm is desired.
- Proficient in Unix/TCL/Perl and possess good communication and presentation skills, along with strong interpersonal skills and problem-solving ability.
Requirements:
Minimum Qualifications:
- 4+ years experience in ASIC physical design.
- Block implementation, extraction, timing, and full-chip design experience.
- Strong communication skills.
- Hands-on TCL/Perl development skills.
Preferred Qualifications:
- Full-chip floorplanning, routing, or timing lead experience for large silicon projects.
- Track record of taping out complex chips on advanced process nodes.
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