IP/SOC verification engineer

2 days ago

Hyderabad, Telangana, India SpanIdea Systems Full time ₹ 15,00,000 - ₹ 25,00,000 per year

About SpanIdea systems:

SpanIdea Systems is a global
product engineering solutions and services company
, headquartered in Bangalore with development centers across India, the US, and Europe. Founded in 2011, the company partners with Fortune 500 clients to deliver solutions in
embedded systems, semiconductors, telecom, networking, IoT, cloud, and mobility
.

With a team of 1000+ professionals, SpanIdea has successfully transformed 100+ product ideas into deployments, combining
R&D, hardware design, verification & validation, and test automation
expertise.

About the role:

We are seeking a
Verification Subject Matter Expert (SME)
to lead SoC verification and design comprehensive verification solutions for next-generation
HBM DRAM products
. This role involves working on highly complex verification environments, requiring innovation and deep technical expertise to deliver best-in-class scalability, quality, and performance.

Verification of HBM products presents unique challenges due to the size and complexity of designs, making this position both demanding and rewarding.

Location: Hyderabad

Experience: 5–8 years

Responsibilities:

  • Develop
    SoC-level test plans
    and analyze coverage.
  • Build advanced
    verification environments
    to verify complex SoCs.
  • Develop
    random/directed tests
    in RTL and GLS environments.
  • Review
    architectural specifications
    for completeness and quality.
  • Collaborate with customers to understand
    verification/validation requirements
    and deliver necessary collateral.
  • Debug and identify root causes/solutions for
    pre-silicon and post-silicon issues
    in HBM architectures.

Qualifications and skill sets:

  • Bachelor's degree
    in Electrical Engineering or related field.
  • 5+ years
    of SoC/IP verification experience.
  • 3+ years
    hands-on experience with:
  • Writing tests & developing verification environments using
    SystemVerilog and UVM
    .
  • Writing
    assertions and coverage
    .
  • Strong expertise with
    SoC simulation tools
    and advanced verification methodologies.
  • Familiarity with
    2.5D/3D package integration
    is a plus.

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