Cloudious - Design Verification Engineer - SoC/System Verilog

3 weeks ago


Hyderabad, Telangana, India Cloudious LLC Full time

Key Responsibilities :

- Own and execute the functional verification of NoC/SoC subsystems, ensuring high-quality IP and SoC-level integration.

- Develop verification plans, testbenches, and assertion-based verification environments using SystemVerilog and UVM.

- Drive test development, regression strategies, and coverage analysis to meet project milestones and quality goals.

- Work closely with architects, RTL designers, and system engineers to understand the design intent and ensure thorough verification coverage.

- Validate standard bus protocols such as AMBA, AXI, AHB, and APB within NoC/SoC environments.

- Debug complex RTL and testbench issues using simulation and waveform analysis tools.

- Maintain and enhance existing verification infrastructure, automate workflows, and contribute to verification best practices.

- Collaborate with cross-functional teams to support pre-silicon and post-silicon validation Skills & Qualifications :

- Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related discipline.

- 5 to 10 years of experience in design verification, particularly in NoC and SoC-based projects.

- Solid expertise in SystemVerilog and UVM methodology for building scalable and reusable verification environments.

- Deep understanding of NoC architecture, routing, flow control, and performance bottlenecks.

- Proven experience in verification of SoC interconnects and subsystems, including protocol verification and integration testing.

- Familiarity with standard AMBA protocols (AXI, AHB, APB) and other on-chip communication standards.

- Proficiency in scripting languages such as Perl, Python, or TCL for automation and tool integration is a strong plus.

- Excellent debugging skills, analytical thinking, and the ability to work independently as well as in a team environment.

- Prior experience in product-based companies and exposure to full-chip verification cycles is highly Attributes :

- Experience with formal verification and assertion-based verification (SVA).

- Exposure to power-aware verification and low-power design methodologies (UPF).

- Familiarity with tools like VCS, Questa, Verdi, DVE, or similar EDA tools.

(ref:hirist.tech)

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