SOC Verification Engineer

4 days ago

Hyderabad, Telangana, India SKYLARK DIGI SOLUTIONS Full time ₹ 3,00,000 - ₹ 5,00,000 per year

Position:
 SOC Verification SME

Location:
 Hyderabad

Openings:
 3

Experience & CTC:

  • 5 to 7 years – Up to ₹30 LPA
  • 7 to 8 years – Up to ₹40 LPA
  • 8 to 10 years – Up to ₹50 LPA
  • Notice Period:
     Immediate to 15 Days

Interview Mode: WALKIN INTERVIEW

Responsibilities:

We're looking for a verification SME, responsible for the SoC verification process and designing comprehensive verification solutions for the next-generation HBM DRAM products.

You will apply your deep understanding of SoC Verification, testbench architecture, SoC verification methodologies, and 2.5D & 3D package integration to understand and analyze bottlenecks and propose innovative solutions to target best in class scalability, quality, testbench performance and verification cycle time. Verification and Testing (validation) of an HBM product are most challenging due to the size of the design and complexity of the functions. They require significant innovation, making this position uniquely exciting. You are a self-motivated, hard-working team player who enjoys working with diverse abilities and backgrounds. You have an innovative approach that is open to improving upon any of our processes or products.


• Develop test plans at SOC Level and analyze Coverage.


• Build verification environments to verify complex SOCs.


• Develop Random/Directed test in RTL and GLS environments.


• Review architectural specifications to ensure high quality.


• Work with customers to understand their verification and validation requirements and provide the necessary collateral.


• Debug and identify root causes and solutions for pre-silicon and post-silicon issues encountered in current HBM products and architectures.

Qualifications


• BS in Electrical Engineering or a related equivalent field.


• relevant experience in SoC/IP verification.


• 5+ years in writing tests and developing verification environments using SystemVerilog and UVM.


• 5+ years of experience with the writing assertions and coverage.


• Strong and relevant expertise with SoC simulation tools and advanced verification methods.

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