IO Layout Design Engineer

Job Title: IO Layout EngineerLocation: BangaloreExperience Required: 3–8 yearsJob Type: ContractJob OverviewWe are looking for an experienced IO Layout Engineer with strong expertise in custom layout design and verification. The ideal candidate should have hands-on experience with advanced technology nodes (28nm and below), deep knowledge of IO design...

We are looking for an experienced IO Layout Engineer to join our team in Bangalore. The role involves custom IO layout design, optimization, and sign-off at advanced technology nodes.Responsibilities:Create and optimize IO circuit layouts including ESD structures and analog IOs.Perform floor planning, placement, routing, and parasitic extraction.Ensure DRC,...

IO LayoutLocation: BangaloreJob Description:Very Good Knowledge on GPIO layouts and performing Layout verifications.Good Exposure to Technologies of GF 55nm , UMC 55nm , TSMC 28nm, TSMC 12nm etc.Should have Solid experience in Layout design and Verifications of all the blocks of a GPIO library like Driver, predriver, receiver, ESD clamps.Should be in...

Position: Analog Layout Design Engineer (SI510FF RM 3682)Required Qualifications:5 to 10 years of experience in analog layout design.Proven experience in advanced nodes (7nm, 5nm, or below) is a must.Proficiency in layout tools such as Cadence Virtuoso, ICV, Calibre, Assura, etc.Strong understanding of analog layout constraints and techniques for...

Purpose:We are seeking a highly skilled and motivated IO Design Expert with deep experience in designing GPIOs, specialty analog/digital IOs, and ESD protection circuits across technology platforms ranging from BCD technologies (e.g., 180nm/130nm/55nm) to advanced CMOS nodes (e.g., 28nm, 16nm, 12nm, 7nm, 5nm). You will play a critical role in the...

Responsibilities:Perform full-custom analog layout for advanced nodes (28nm and below FinFET/CMOS technologies).Work on block-level and top-level layouts of circuits such as:PLLs, ADCs, DACs, LDOs, Bandgaps, High-speed IOs, SerDes, RF blocks

Key Responsibilities: Include the development and preparation of multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Working on layout design of owned blocks with Cadence Virtuoso XL.Working on block and top-level level layout verification with Calibre.Extensive PAD...

Hiring iOS Test Engineer (Automation), 25 yrs exp, Bangalore (onsite). Must have Appium, Xcode, iOS SDK, CI/CD exp. Apply now for in-person interviewShare your resume at -

Memory LayoutRole: Layout Design of SRAM/CAM/RF compiler memories in 5/3FF technology.Responsibilities: Development of key building blocks of memory architecture such as Row Decoder, IO, Control. Skilled in pitched layout concepts, floor planning for Placement, Power and Global Routing. Compiler level integration, verification of Compiler/Custom...

Roles & Responsibilities: Custom layout development on block level to Top level I/O layout for GPIO, HSTL, HCSL, VTMON, LVCMOS, DDR, LVDS etc., Need knowledge on Latchup, ESD and EM. Exposure to lower nodes N3E, 5nm etc.,SKILL: LVS/DRC/ERC/Litho Checks/Antenna/ESD-LU/Density etc.  Should possess good knowledge on CMOS functionality, CMOS fabrication...