Design Verification Engineer
2 weeks ago
Description :
Job Title : Design Verification Engineer.
Location : Bangalore.
Experience : 6+ Years.
Job Description :
We are seeking experienced Design Verification Engineers with strong expertise in SystemVerilog-based testbench development using OVM/UVM methodology.
The ideal candidate will have hands-on experience in verifying high-speed interfaces like USB 3.2 and DisplayPort v1.4, including writing test cases, developing UVCs, and handling error scenarios.
Key Responsibilities :
- Develop complex testbenches in SystemVerilog using OVM/UVM methodology.
- Identify and implement features and functionalities for USB 3.2 and DisplayPort v1.4 protocols.
- Develop USB 3.2 UVC with robust error handling mechanisms.
- Update DisplayPort UVC with new features and enhancements.
- Write and maintain test cases for USB 3.2, DisplayPort 1.4, and AUX channels.
- Collaborate with design and verification teams to ensure thorough functional coverage.
- Debug, simulate, and validate verification environments and test scenarios.
Technical Skills Required :
- Strong hands-on experience in SystemVerilog, OVM/UVM methodology.
- Experience with USB 3.2 and DisplayPort 1.4 protocols.
- Testbench development, UVC creation, and error handling in verification environments.
- Writing functional test cases and performing coverage analysis.
- Familiarity with simulation and verification tools used in high-speed interface verification.
Soft Skills / Competencies :
- Strong analytical and problem-solving skills.
- Good communication and teamwork abilities.
- Ability to work independently and manage multiple verification tasks.
- Quick learner and adaptable to new protocols and methodologies.
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