Functional Verification Engineer

2 days ago

Hyderabad, Telangana, India Proxelera Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Job Title:
Functional Verification Engineer

Location:
Hyderabad

Work Mode:
Work From Office (WFO)

Role Summary

We are looking for an experienced
Functional Verification Engineer
with strong hands-on expertise in
SystemVerilog/UVM
. The ideal candidate will be proactive, self-driven, and capable of independently managing deliverables while working on block-level and IP-level verification.

Key Responsibilities

  • Develop and maintain
    block-level testbenches
    using SystemVerilog/UVM.
  • Create and execute
    verification plans (V-Plans)
    , run regressions, and drive
    coverage closure
    .
  • Work on testbenches with
    Real Number Modelling (RNM)
    .
  • Perform
    netlist and gate-level simulations (GLS)
    .

Qualifications & Experience

  • Education:
    Bachelor's degree or higher in Electronics or related field.
  • Experience:
    5–10 years in Functional Verification.

Technical Skills

  • Strong hands-on coding experience in
    SystemVerilog/UVM
    .
  • Proven experience in
    block/IP-level verification
    ; subsystem/SoC-level experience is an added advantage.

Soft Skills

  • Strong communication skills.
  • Ability to work independently and meet delivery schedules.

Strict Checklist (Must-Have Requirements)

Pure DV role with expertise in developing TB environments and components

GLS experience:
0-delay and timing simulations

Experience in integrating
Real Number Models
into the TB and running digital simulations

Strong experience in
IP verification coverage closure
(100% code + 100% functional coverage)

Typically expected in engineers with
6+ years
of DV experience

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