GPU Functional Verification Sr Lead Engineer

4 days ago

Bengaluru, Karnataka, India Qualcomm Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Minimum Qualifications:


• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

  • In the role of GPU Functional Verification Engineer, your project responsibilities will include the following,

    • Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces

    • Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices

    • Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality

    • Collaborate with worldwide architecture, design, and systems teams to achieve all project goals

    • Currently, we are looking for candidates who can match one or more of the profiles listed below,

    • Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver

    The pre-Si verification team in Bangalore is currently heavily involved in the following

    • UVM/SV based constrained random test bench for functional verification

    • Subsystem level TB for complete GPU workload analysis and compliance

    • Emulation platforms to analyze performance and pipeline bottlenecks

    • Formal tools – both for reduced time to bug & property based FV sign-off

    • Power Aware & Gate level simulations to deliver a high-quality GPU implementation

    • Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug

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If you would like more information about this role, please contact Qualcomm Careers.

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