Functional Verification Engineer

2 days ago

Hyderabad, Telangana, India Luxoft Full time ₹ 6,00,000 - ₹ 12,00,000 per year
Project description

We are seeking an experienced Functional Verification Engineer with strong expertise in System Verilog/UVM to develop and maintain verification environments for block-level and IP-level designs. The ideal candidate will be proactive, self-driven, and capable of managing deliverables independently.

Responsibilities

Develop and maintain block-level verification environments and testbenches using SystemVerilog/UVM.

Create and execute verification plans (VPlans), run regressions, and drive coverage closure.

Implement and verify designs using real number modeling (RNM) for mixed-signal interfaces.

Perform netlist and gate-level simulations (GLS) to validate post-synthesis and post-layout functionality.

Debug functional and testbench issues, ensuring high-quality, reusable verification components.

Skills

Must have

5-10y exp

Develop and maintain block-level testbenches using System Verilog/UVM.

Create and execute verification plans (Vplan), run regressions, and achieve coverage closure.

Work on testbenches with real number modeling.

Perform netlist and gate-level simulations.

Hands-on coding in SystemVerilog/UVM.

Nice to have

Experience with block/IP-level verification; subsystem or SoC-level experience is a plus.

Soft Skills: Strong communication, ability to work independently and meet schedules.

Other

Languages

English: B2 Upper Intermediate

Seniority

Regular

Hyderabad, IN, India

Req. VR-118999

Manual Testing

Automotive Industry

12/11/2025

Req. VR-118999

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