Senior DFT Engineer

11 hours ago

Bengaluru, Karnataka, India Hire Wings Full time ₹ 15,00,000 - ₹ 28,00,000 per year

Role & responsibilities

We are seeking an experienced Senior Design for Testability (DFT) Engineer with a proven track record in implementing and optimizing DFT methodologies for complex SoCs and ASICs. The ideal candidate will have deep expertise in scan insertion, ATPG, MBIST, and JTAG along with strong knowledge of ASIC design flows and tape-out processes

  • Drive and own DFT architecture, planning, and implementation for large SoCs/ASICs.
  • Perform scan insertion, ATPG (Stuck-at, At-Speed, Transition faults), and pattern simulation/debug.
  • Implement and verify MBIST, JTAG, boundary scan across multiple blocks and top level.
  • Ensure timing closure and STA support for DFT modes in collaboration with design and PnR teams.
  • Develop and optimize test strategies to maximize fault coverage and minimize test cost.
  • Collaborate with silicon validation and ATE teams to ensure smooth bring-up and debug.
  • Automate DFT flows using scripting (Perl, TCL, Python, Shell) for productivity improvements.
  • Provide technical mentorship and guidance to junior engineers.

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Preferred candidate profile

  • Experience: 8+ years in DFT design and implementation.
  • Education: B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or VLSI Engineering.
  • Technical Skills:
  • Strong hands-on with industry-standard tools: Synopsys DFT Compiler, Tessent, Tetramax, Spyglass, VCS, Verdi.
  • Expertise in Scan, ATPG, MBIST, JTAG, OCC/EDT methodologies.
  • Good understanding of ASIC/SoC flow, STA, synthesis, tape-out processes.
  • Strong debugging skills for DRC/coverage violations.

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