Design Implementation Engineer, Staff

Company:Qualcomm India Private LimitedJob Area:Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FNetwork-on-chip (NoC)/ Interconnect  implementation  for the next generation System-on-chip (SoC) for smartphones, notebooks, smart glasses, tablets and other product categories. The roles and responsibilities for this position includes but not limited to:-Design implementation for Next-gen Qualcomm coherent and non-coherent interconnect fabricResponsible for Floor planning, design optimization for synthesis and PD  for all the Qualcomm  interconnectsPartner with NoC design team to improve micro architecture to ensure the design meets all implementation requirements.Actively work with SoC Architecture, physical design team, Soc Floorplan, core teams and various other interconnect teams in various other sitesWill be part of BDC infrastructure (NoC/Interconnect) core teamWorking with design and DFT teams on understanding design in context of physical design timing closure and power optimizationWorking across teams to align on important areas of PPA improvement and ensure targets are met; ensures designs are innovative and compatible with highest standards.Manage SoC dependencies, planning and tracking of all back-end design related tasksGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.Minimum Qualifications:• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.10+ years of solid experience in IP/SoC implementationExpertise in digital flow design implementation RTL to GDSKnowledge of ASIC back-end design flows and methods and tools (Design compiler,PrimeTime, ICC2, Innovus, )understanding of STA and timing closure methodologies, including effect on congestion/routing/power.Knowledge of entire PD flow from netlist to GDS (Floorplanning, Power planning, Placement/CTS/Routing and corresponding optimization steps).Have experience in driving timing convergence at Chip-level and Hard-Macro levelUnderstanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC conceptsknowledge of Digital Design and RTL developmentUnderstanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.Working knowledge of Lint, CDC, PLDRC, CLP etcGood understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verificationExperience in driving the project milestones across the design, verification and physical implementationsShould possess effective communication and leadership skillsExperience in design automation using TCL/Perl/Python. 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