STA Design Engineer

24 hours ago


Bengaluru, Karnataka, India Techno Facts Solutions Full time ₹ 15,00,000 - ₹ 25,00,000 per year

Job Title: STA Design Engineer (Backend)

Location: Bangalore

Experience: 5+ Years

Job Description:

We are looking for an experienced STA Design Engineer with strong expertise in Static Timing Analysis (STA) for ASIC/SoC backend design. The candidate should have hands-on experience in timing closure, signoff methodologies, and working closely with physical design and RTL design teams to deliver high-quality silicon.

Key Responsibilities:

  • Perform Static Timing Analysis (STA) across multiple process, voltage, and temperature (PVT) corners.
  • Drive timing closure at block and full-chip level.
  • Work on constraint development, validation, and optimization (SDC files).
  • Perform setup, hold, recovery, and removal checks for timing signoff.
  • Debug and resolve timing violations (setup/hold, crosstalk, IR drop related).
  • Collaborate with physical design, synthesis, and RTL teams to achieve timing closure.
  • Work with signoff tools to ensure design meets timing, noise, and power integrity requirements.
  • Generate and maintain STA reports for signoff review.

Expertise / Skills Required:

  • 5+ years of experience in STA / backend design.
  • Strong expertise in STA tools (Synopsys PrimeTime / Cadence Tempus or equivalent).
  • Good understanding of ASIC/SoC design flow (RTL to GDSII).
  • Proficiency in timing constraints (SDC) development and validation.
  • Knowledge of clock tree synthesis (CTS) and timing ECOs.
  • Exposure to parasitic extraction (SPEF) and impact on timing.
  • Strong debugging skills for setup/hold violations.
  • Scripting skills in TCL, Perl, or Python for automation.
  • Good communication and collaboration skills with cross-functional teams.

Good to Have:

  • Experience with low-power design techniques (UPF/CPF).
  • Knowledge of signal integrity / crosstalk analysis.
  • Exposure to physical design flow (PnR).

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