DFT Manager

2 weeks ago

Bengaluru, Karnataka, India MIPS Full time ₹ 20,00,000 - ₹ 25,00,000 per year

About MIPS
MIPS is a leader in high-performance RISC-V CPU IP, enabling innovation across automotive, AI, data center, and embedded markets. Our engineering teams are building the next generation of compute solutions, and we are looking for passionate talent to join us in shaping the future of semiconductors.

Position Overview
The DFT Manager leads and develops the engineering team responsible for designing and deploying advanced Design-for-Test solutions in semiconductor chip development. This role focuses on building robust DFT architectures—including ATPG, MBIST, LBIST, analog test solutions—and implements repeatable methodologies and flows that ensure rapid, optimized test pattern generation and efficient project execution.

Key Responsibilities

  • Lead, mentor, and manage the DFT engineering team, overseeing daily operations and technical development.
  • Define and deploy DFT architecture for chips with features such as Automatic Test Pattern Generation (ATPG), Memory Built-In Self-Test (MBIST), Logic Built-In Self-Test (LBIST), and analog test solutions.
  • Develop and optimize test pattern generation methodologies, prioritizing test time reduction and manufacturing efficiency.
  • Establish and maintain standardized, repeatable DFT methodologies and flows to consistently achieve fast turnaround and reliable results across projects.
  • Collaborate cross-functionally to integrate DFT features and requirements throughout the silicon development lifecycle.
  • Automate test program, script development for maximum coverage and reduced test cost.
  • Continuously analyze test performance data and apply lessons learned for iterative improvement.
  • Promote innovation and continuous improvement by evaluating new trends, tools, and best practices.
  • Document DFT specifications, standards, and re-use strategies for knowledge sharing and future use.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of hands-on DFT experience plus proven leadership of DFT teams on SoCs.
  • Expertise in test pattern generation, ATPG, MBIST, LBIST, analog test development, and scan insertion.
  • Significant experience optimizing test time through efficient DFT strategies and tool use.
  • Proven ability to design and implement repeatable DFT flows and reusable test IP.
  • Proficiency with EDA tools (Synopsys, Cadence, Mentor Graphics), and scripting (Python, Perl, TCL).
  • Strong analytical, organizational, leadership, and communication skills.

Desired Attributes

  • Strategic thinker who translates customer, product requirements into practical, innovative test solutions.
  • Inspirational leader focused on team growth, technical excellence, and methodology re-use.
  • Proactive, detail-oriented professional committed to efficiency, quality, and process improvement.

Why Join MIPS?

  • Be part of a team driving innovation in RISC-V CPU IP and SoC development.
  • Work on cutting-edge semiconductor designs with global impact.
  • Collaborative, growth-focused environment with opportunities for innovation and leadership.

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