Senior DFT Engineer, SSG

The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge.

Work hard. Have fun. Make history.

We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production.

As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability — from early DFT architecture planning to high-volume silicon bring-up and yield ramp.

Key job responsibilities
Key job responsibilities
 Lead development & implementation of DFT architecture including system level DFT for a full chip
 Write and guide others in writing design flow and project documentation.
 Own DFT planning, milestone tracking, and cross-functional checklist reviews.
 Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists.
 Review and sign-off SoC level DFT mode timing closure using static timing analysis
 Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon
 Keep informed on and introduce new technology into Design-for-Test process as appropriate.

Basic Qualifications:
- Bachelor's degree in Electrical Engineering or a related field
- 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT.
- Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production.
- DFT Architecture Expertise: Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: Scan architecture, compression, and ATPG implementation for high fault coverage and test quality.
- MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration.
- IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures.
- DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths.
- RTL and gate-level debug, including mismatch triage and simulation correlation. Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation. Tool Proficiency: Deep hands-on experience with Tessent / Industry Std EDA tools, including: IJTAG ICL extraction and PDL modeling.
- DFT logic insertion, pattern generation, and diagnostics. Design Background
- Experience in writing verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets.
- Pattern validation, format conversion, and debugging across wafer sort and final test. Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements.
- Silicon Debug: Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis. Automation Skills:
- Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl. Collaboration: Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing. Execution Excellence: Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success.

Preferred Qualifications:
- Master's degree or Ph.D. degree in Electrical Engineering or related field
- Leadership: Led multi-site/global DFT teams, mentoring engineers and managing design reviews.
- Drove design-for-test planning in collaboration with customers or design services partners.
- Technical Depth: Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies.
- Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues.
- Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement.

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