Verification Methodology Architect
2 days ago
About the Role:
We are seeking a highly experienced Verification Engineer to join our dynamic team, driving innovation in advanced verification methodologies for complex semiconductor designs. You will play a key role in architecting, developing, and deploying verification methodologies for industry-leading IPs and sub-systems.
Key Responsibilities:
- Lead the deployment of verification tools, platforms, and strategies for complex IPs
- Drive simulation-based and hardware-assisted verification efforts, including debugging and root cause analysis
- Apply expertise in a broad range of verification technologies, including simulation, static, and formal verification
- Develop and enhance verification methodologies, including verification cockpits and CAD flows
- Collaborate cross-functionally with IP design and DV teams as well as tools teams to ensure product quality
- Mentor and guide junior engineers, fostering a culture of technical excellence
Qualifications:
- 10+ years
of experience in verification engineering for complex hardware systems - Deep expertise in simulation and debug, with a proven track record of silicon success
- Hands-on experience with Static/ Formal verification tools and methodologies
- Experience developing and deploying verification methodologies, including verification cockpits and CAD flows
- Exposure to hardware-assisted verification environments (FPGA prototyping, emulation) is a strong plus
- Strong analytical, problem-solving, and communication skills
- Bachelor's or Master's in Electrical Engineering, Computer Engineering, or related field
- Familiarity with industry-standard verification languages (SystemVerilog, UVM, SVA)
- Experience with scripting and automation (Python, Perl, TCL)
- Track record of technical leadership and cross-functional collaboration
Why Synopsys:
Join a team that powers innovation and values agility, courage, excellence, and trust. We offer opportunities to work on cutting-edge technology and make a real impact.
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