
Lead Design Verification
3 weeks ago
Key Responsibilities:
- Lead the creation and execution of comprehensive verification strategies using industry-leading methodologies such as UVM.
- Architect and develop sophisticated verification environments (testbenches) to achieve optimal code coverage and functionality.
- Utilize advanced simulation tools, including ModelSim, Cadence Incisive, and Synopsys VCS, to validate RTL designs.
- Diagnose and resolve complex verification issues, collaborating with design engineers to ensure design integrity.
- Conduct thorough code reviews and enforce adherence to verification best practices and coding standards.
- Mentor junior engineers, fostering a culture of continuous learning and improvement within the team.
- Stay abreast of emerging verification technologies and methodologies, driving innovation and efficiency in verification processes.
Qualifications:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related discipline.
- Extensive experience (5+ years) in design verification for ASICs or SoCs, with a proven track record of successful project delivery.
- Deep understanding of digital design principles and verification methodologies, particularly UVM.
- Proficiency in hardware description languages such as Verilog or VHDL, and scripting languages like Python or Perl.
- Strong analytical skills and a methodical approach to problem-solving.
- Excellent leadership and communication skills, with the ability to collaborate effectively across teams.
Benefits:
- Competitive compensation package, including comprehensive health benefits and retirement plans.
- Opportunity to work on innovative projects in a collaborative and forward-thinking environment.
- Support for professional development and career progression, with access to continuous learning resources.
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