Design Verification Lead
2 weeks ago
Key Responsibilities:
- Develop verification plans and build test benches to enable IP/sub-stem/SoC level verification.
- Create functional tests based on verification test plans.
- Drive design verification to closure based on defined verification metrics, including test plan, functional, and code coverage.
- Debug, root-cause, and resolve functional failures in the design, partnering with the Design team.
Requirements:
- Bachelor's or Master's degree in Computer Science, Electronics Engineering, or equivalent practical experience.
- 8/10+ years of hands-on experience in StemVerilog/UVM methodology and/or C/C++ based verification.
- 8/10+ years of experience in IP/sub-stem and/or SoC level verification based on StemVerilog UVM/OVM methodologies.
- Experience in developing UVM-based verification environments from scratch.
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
- Experience with verification of ARM/RISC-V based CPU sub-stems or SoCs.
- Experience with IP or integration verification along with expertise in protocols like AMBA, PCIe, DDR, USB, Ethernet.
- Experience in E tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments.
- Experience with revision control systems like Mercurial(Hg), Git, or SVN.
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