Design and verification engineer

2 weeks ago


Bengaluru, Karnataka, India L&T Technology Services Full time ₹ 15,00,000 - ₹ 20,00,000 per year

Job Description DV Positions:Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification

Develop functional tests based on verification test plan

Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage

Debug, root-cause and resolve functional failures in the design, partnering with the Design team Qualifications and Skills for DV Positions:Bachelor's or Masters degree in Computer Science, Electronics Engineering or equivalent practical experience5+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies

Experience in development of UVM based verification environments from scratch

Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle

Experience with verification of ARM/RISC-V based CPU sub-systems or SoCsExperience with IP or integration verification along with expertise of protocols like AMBA, PCIe, DDR, USB, EthernetExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Experience with revision control systems like Mercurial(Hg), Git or SVN



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