Senior ASIC RTL Engineer, Core IP

2 weeks ago

Bengaluru, Karnataka, India Google Full time ₹ 12,00,000 - ₹ 36,00,000 per year

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
  • Experience with ASIC design methodologies and QA flows (Lint, CDC, RDC, VCLP), defining design constraints (SDC) and Low-power intent (UPF).

Preferred qualifications:

  • Master's or PhD degree in Electrical Engineering, Computer Engineering or Computer Science.
  • Experience with a scripting language like Perl or Python.
  • Experience in design and development of audio blocks or Mobile Industry Processor Interface (MIPI) display or camera sub-systems.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

  • Perform Verilog/SystemVerilog Register-Transfer Level (RTL) coding, functional/performance simulation debug and Lint/Cyber Defense Center (CDC)/VCLP checks.
  • Participate in test planning and coverage analysis.
  • Develop RTL implementations that meet engaged power, performance and area goals.
  • Participate in synthesis, timing/power closure and support pre-silicon and post-silicon bring-up.
  • Work with multi-disciplined and multi-site teams in Architecture, RTL design, verification, Design for Test (DFT) and Physical Desig (PD).

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

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