Technologies - Principal DFT Engineer - MBIST/SoC

Key Responsibilities:Develop and implement DFT architecture with a focus on MBIST for advanced SoCs.Integrate MBIST IPs, generate test insertion and verification infrastructure.Work on DFT planning, insertion, simulation, and pattern generation.Perform ATPG and MBIST pattern generation and debug failures from silicon bring-up.Collaborate with RTL, Physical...

Company: Eteros Technologies India Private LimitedEteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad• Our world-wide customers are amongst The Who's...

We're looking for an engineer with a minimum of 6 years of experience in the DFT domain, including at least 4 years specializing in Memory Built-In Self-Test (MBIST) methodologies.The ideal candidate will have hands-on experience with MBIST insertion at the Block/SoC level.Proficient in MBIST pattern generation, fault simulation, and test development for...

Job Title: PrincipalDFT EngineerJob Location: Bangalore, India (This position requires a full-time, on-site presence in our Bangalore, India office)Job ID: AI2436Job Description:Key Responsibilities:Block-level, Sub-system, and SOC DFT architecture and methodology definition including SCAN, MBIST, IP tests, JTAG.Lead DFT architecture and implementation for...

We are looking for an experienced DFT Lead / Architect with a proven track record of DFT architecture, implementation and verification at SoC level. The ideal candidate will have the ability to build and lead a high-performing DFT team while delivering world-class DFT solutions for complex chips.Key ResponsibilitiesDFT Architecture & StrategyDefine and...

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Role : DFT Engineer.Location : Bangalore (work from office).Experience : 5+ years.Job Description : We are looking for an energetic, passionate and process oriented DFT Engineers who has extensive experience in planning, implementation and verification of DFT features for multiple SoC. Direct Responsibilities of the role, but not limited to : ...

ResponsibilitiesDefine and implement the DFT architecture, flow, and methodology for complex SoCs, including scan insertion, MBIST, boundary scan, and IP testing.Analyse digital DFT metrics to evaluate test time, yield, and defect rates.Collaborate with RTL designers, physical design, and verification teams to ensure seamless DFT integration and timing...

Role & responsibilitiesWe are seeking an experienced Senior Design for Testability (DFT) Engineer with a proven track record in implementing and optimizing DFT methodologies for complex SoCs and ASICs. The ideal candidate will have deep expertise in scan insertion, ATPG, MBIST, and JTAG along with strong knowledge of ASIC design flows and tape-out...

Position: DFT engineers (SI46FT RM 3676)Job Description:We are seeking experienced DFT Engineers with strong expertise in Scan, ATPG, and MBIST for SoC/ASIC designs. The role focuses on implementation, pattern generation, and verification of DFT features to ensure high test coverage and silicon readiness.Key Responsibilities:Implement and verify Scan, ATPG,...