Design Verification Engineer
5 days ago
JD:
Working on Ethernet MAC Application Layer Verification.
System Verilog/UVM
Working on Ethernet SERDES MAC/PCS Subsystem
Subsystem supports 100GE/200GE/400Ge.
Knowledge of Ethernet protocols
AN Markers and their verification, SOP/EOP protocol checking
Ethernet Error scenarios, Coverage closure
Job Type: Full-time
Pay: ₹2,000, ₹2,500,000.00 per year
Experience:
- System Verilog/UVM: 5 years (Preferred)
- Ethernet MAC Application Layer Verification: 5 years (Preferred)
Work Location: Remote
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