Design Testability Engineer

4 days ago

Bengaluru Chennai Hyderabad, India ti Steps Full time ₹ 8,00,000 - ₹ 12,00,000 per year

About the Role:

We are seeking a skilled and detail-oriented Design Testability Engineer (DFT Engineer) to join our hardware design team. The ideal candidate will be responsible for developing and implementing Design for Test (DFT) strategies for complex SoCs, ASICs, or IC designs to ensure high-quality and efficient silicon testing and validation.

Key Responsibilities:

  • Develop and implement DFT architecture and methodologies for ASIC/SoC designs.
  • Design and integrate scan chains, boundary scan (JTAG), MBIST, and LBIST into digital designs.
  • Collaborate with RTL design, synthesis, and physical design teams to ensure testability requirements are met.
  • Perform test coverage analysis and optimize DFT insertion to achieve desired coverage metrics.
  • Generate and validate test patterns using ATPG (Automatic Test Pattern Generation) tools.
  • Work on silicon bring-up, validation, and failure analysis during post-silicon testing.
  • Support ATE (Automated Test Equipment) pattern generation, simulation, and debugging.
  • Participate in DFT verification to ensure correct scan insertion, compression, and pattern simulation.
  • Analyze test results and debug DFT-related issues at chip and board levels.

Preferred Skills :

  • Experience with scan compression, boundary scan insertion, or test point insertion techniques.
  • Knowledge of low-power DFT strategies (for multi-voltage and multi-domain designs).
  • Familiarity with DFM (Design for Manufacturability) and yield improvement techniques.
  • Experience in post-silicon validation and ATE environments (Advantest, Teradyne, etc.).

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