DFT Lead

Location: BangaloreExperience: 10+/12+/15+yrsMust Have Skills: DFT, Scan Insertion (Must), ATPG, JTAGRole Overview:We are looking for aDFT Leadwith deep expertise in scan insertion, ATPG, and JTAG to take ownership of DFT strategy and implementation across multiple SoC and ASIC projects. This role demands leadership, architectural decision-making, and...

Role: DFT LeadExperience:10+ yearsLocation: BangaloreSalary: Can be discussedJob DescriptionWe are looking for an energetic, passionate and process oriented DFT Leads who has extensive experience in planning, implementation and verification of DFT features for multiple SoC.Direct Responsibilities of the role, but not limited to,working on various aspects of...

Hiring DFT Lead (10–20 yrs) with expertise in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, and strong leadership skills. Required Candidate profileExperienced DFT Lead (10–20 yrs) skilled in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, debugging, and...

Lead Soc is hiring DFT LeadersHands on experience working in DFT with scan insertion.Good communication and analytical skills and Team handling.Experience: 9 years to 20 yearsLocation: BangalorePlease share your profile to for further discussion

Job Title:Lead DFT EngineerExperience:7+ YearsLocation:BangaloreEmployment Type:Full-timeIndustry:Semiconductors / ASIC / SoC DesignJob Summary:We are looking for aLead DFT Engineerto drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional...

Design for Testability (DFT) Engineer (Senior Level - 10+ years’ experience)Job Summary:We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a mastery of DFT methodologies and the ability to drive the...

Open position:- Lead DFT EngineerExperience: - 7+ yearsLocation:- BangaloreNP: - Immediate to 15 daysJD: -Experience with DFT tools such as Synopsys DFT Compiler, Test Kompress and Xelium.Minimum 7+ years of experience in DFT engineering, with a focus on Scan Insertion and ATPG, ICL, SSNStrong knowledge of DFT techniques such as Scan Chains, ATPG, Boundary...

Greetings From Tessolve Semiconductors.A widely leading core semiconductor company in world wide.We Are Hiring ..Engineers who's having strong experience and eager to learn advanced IC Design techniques.We Hiring DFT Engineers for our current project requirement with ATPG, SCAN & MBIST ExpertiseKindly Follow the below JD -DFT - MBIST RequirementsExperience -...

Key skills with hand on: DFT, MBIST, Scan Insertion, ATPG, Full Chip ,SOC ,VLSIExperience: 5 - 25 yearsWork Location: Trivandrum, Bangalore, Hyderabad, Chennai, PuneEducation: Engineering (excluding Mechanical/Civil)Detailed JD:5+ years' experience in ASIC/DFT - simulation and Silicon validation, •Should have worked in at least one Full chip DFT...

DFT Lead :Work Location - BangaloreExperience - 7+ YearsDesired Skills and Experience –· 7+ years of experience/concept on all aspects of DFT i.e. SCAN/ATPG, MBIST, Boundary Scan.· DFT logic integration and verification.· Experience in debugging low coverage and DRC fixes· Gate Level ATPG simulation with and without timing.· Pattern generation,...