DFT Lead

Role: DFT LeadExperience:10+ yearsLocation: BangaloreSalary: Can be discussedJob DescriptionWe are looking for an energetic, passionate and process oriented DFT Leads who has extensive experience in planning, implementation and verification of DFT features for multiple SoC.Direct Responsibilities of the role, but not limited to,working on various aspects of...

We're hiring a DFT Lead with 10+ years of experience in VLSI front-end design. The role involves DFT architecture, ATPG, scan insertion, STA, timing closure, and debug. Strong scripting and communication skills are essential. Required Candidate profileExperienced DFT professional skilled in ATPG, scan insertion, and timing closure. Proven ability to lead...

Hiring DFT Lead (10–20 yrs) with expertise in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, and strong leadership skills. Required Candidate profileExperienced DFT Lead (10–20 yrs) skilled in ATPG, Scan/MBIST/JTAG, pattern validation, Synopsys/Cadence/Mentor tools, Perl/TCL scripting, debugging, and...

Job Requirements Job Title: Senior DFT Lead EngineerJob Type: Full-Time We are currently seeking a Senior DFT Lead Engineer with expertise in SCAN, ATPG, and BIST. As the ideal candidate, you will be responsible for leading the DFT efforts within our team, ensuring the successful implementation of design-for-test methodologies. Your role will involve...

Job Title:Lead DFT EngineerExperience:7+ YearsLocation:BangaloreEmployment Type:Full-timeIndustry:Semiconductors / ASIC / SoC DesignJob Summary:We are looking for aLead DFT Engineerto drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional...

Tessent DFT LeadExperience- 10+ YearsJob Location -BangaloreHands on experience in Tessent DFT RTL insertion, DRC checks and debug is a must.Hands on experience on Scan Insertion, ATPG, GLS debug, MBIST pattern generation and validation.Working knowledge of timing enabled GLS and related debug.A basic understanding of DFT IPs like OCC, EDT, SSN, MBIST...

Job Description-The candidate is expected to have clear understanding of IJTAG, P1500 protocols and should have hands on experience of at least one of these.The candidate is expected to have clear understanding of BSCAN,MBIST, SCAN, ATPG and Simulation concepts.Must be hands-on with MBIST insertion, Scan Insertion, ATPG pattern generation and simulations,...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and...

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and...

Position: DFT EngineerExperience: 5+ years Location: Bangalore, India Company: Mettlesemi Systems and Technologies Pvt Ltd Job Type: Full-TimeWe are seeking a skilled Design-for-Test (DFT) Engineer to join our silicon design team for a high-impact engagement with a prestigious global client. The ideal candidate will have strong expertise in SoC-level DFT...