STA Lead

1 week ago

Bengaluru, Karnataka, India Team Computers Full time US$ 1,25,000 - US$ 1,75,000 per year

We are seeking an experienced Full-Chip STA Engineer to drive timing closure and sign-off across the entire SoC/ASIC design. The role requires expertise in multi-block integration, multi-mode/multi-corner analysis, and sign-off methodology for advanced technology nodes.

Key Responsibilities:

  • Perform full-chip static timing analysis for all functional and test modes across multiple PVT corners.
  • Own SDC constraint generation, validation, and refinement at top-level.
  • Collaborate with block-level STA, physical design, synthesis, and clock teams to achieve timing closure.
  • Debug and resolve full-chip setup/hold violations through ECOs, floorplan changes, and clock optimizations.
  • Conduct MMMC (Multi-Mode, Multi-Corner) timing analysis, including OCV, AOCV, and POCV variations.
  • Integrate timing reports from multiple blocks, perform hierarchical timing closure, and ensure sign-off compliance.
  • Work with DFT teams to analyze scan shift and at-speed test timing.
  • Automate report generation, violation tracking, and closure metrics using Tcl, Perl, or Python.
  • Provide guidance on timing budgets for IP/block owners.
  • Interface with foundries and EDA vendors to resolve tool and library issues.

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