STA Lead

Job DescriptionKEY RESPONSIBILITIES:Responsible for Multi Voltage domain STA environment setup, execution and timing closureDrive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using...

Skills RequiredNetlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and...

We're Hiring: STA Engineer | 5–10 Years Experience | Bangalore & HyderabadCompany:ACL Digital CompanyLocation:Bangalore & HyderabadExperience:5 to 15 YearsJob Type:Full-TimeACL Digitalis looking forSenior Static Timing Analysis (STA) Engineerswith solid experience in timing closure of advanced SoC designs.If you're an STA expert who thrives in fast-paced,...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill...

Job DescriptionKey Responsibilities:Timing Analysis & ClosurePerform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels.Achieve timing closure by resolving violations and optimizing paths.Constraint DevelopmentDefine and validate timing constraints (clocks, I/O delays, false/multi-cycle paths).Integrate constraints from multiple IPs...

Role & responsibilitiesPerform full-chip static timing analysis for all functional and test modes across multiple PVTcorners.• Own SDC constraint generation, validation, and refinement at top-level.• Collaborate with block-level STA, physical design, synthesis, and clock teams to achievetiming closure.• Debug and resolve full-chip setup/hold violations...

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high...

Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

Job Description:We are looking for a Lead STA (Static Timing Analysis) Engineer to join our semiconductor design team. The ideal candidate will have extensive experience in ASIC/SoC timing analysis, closure, and signoff, along with deep knowledge of industry-standard tools like PrimeTime or Tempus.You will be responsible for driving timing closure, ensuring...

General Summary:As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits,...