Sta Engineer
2 days ago
Job Description:
We are looking for a Lead STA (Static Timing Analysis) Engineer to join our semiconductor design team.
The ideal candidate will have extensive experience in ASIC/SoC timing analysis, closure, and signoff, along with deep knowledge of industry-standard tools like PrimeTime or Tempus.
You will be responsible for driving timing closure, ensuring robust design constraints, and collaborating with Physical Design, Synthesis, and Signoff teams to deliver high-performance silicon.
Roles and Responsibilities:
- Perform Static Timing Analysis (STA) across multiple corners and modes (MMMC).
- Debug and resolve setup, hold, recovery, and removal violations.
- Own and maintain timing constraint files (SDC) throughout the flow.
- Drive timing closure from pre-CTS to post-route and final signoff stages.
- Work with Physical Design and RTL teams to fix timing through ECO implementation.
- Conduct timing correlation and path-based analysis between synthesis and post-route stages.
- Collaborate with cross-functional teams Clock, Power, DFT, RTL, and Signoff engineers.
- Support signoff timing verification and ensure design meets PPA (Performance, Power, Area) goals.
- Develop TCL/Perl/Python scripts to automate timing report generation and analysis.
- Provide detailed timing closure reports and updates to project managers and stakeholders.
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