Lead AMS PHY Expert

2 days ago

Bengaluru, Karnataka, India L&T Semiconductor Technologies Full time ₹ 15,00,000 - ₹ 20,00,000 per year

Purpose:We are seeking a highly experienced and innovative PHY (Physical Layer) Design Expert with deep expertise in high-speed interface technologies, including USB (2.0/3.x/4.0), Ethernet (10/100/1000/10GBASE-T), and MIPI (D-PHY, C-PHY). This role requires a strong technical leader who can drive advanced PHY development, foster innovation, and mentor junior engineers. You will work at the forefront of connectivity technology, contributing to next-generation SoC solutions.

Areas Of Responsibility:Architect the PHY to arrive at the optimized design partitioning, specification of Analog and Digital portions of the PHY.Lead the design, simulation, and verification of high-speed PHYs (USB, Ethernet, MIPI) for ASIC and SoC integration. Work with cross-functional teams (architecture, layout, digital, firmware) to ensure robust and optimized PHY performance.

Perform signal integrity (SI) and power integrity (PI) analysis. Own or contribute to specification development, IP integration, and bring-up activities in silicon. Collaborate with board and system teams to define and validate interface standards and compliance.

Mentor and guide junior engineers, promoting knowledge sharing, technical growth, and team development. Contribute to a culture of innovation, research, and continuous improvement in PHY design methodologies. Engage in technical reviews, design audits, and IP quality assessmentExperience and Qualification:Bachelor's or master's degree in electrical engineering or related field; PhD is a plus.15+ years of experience in high-speed PHY architecture, design, AMS/DMS verification, qualification.

Deep expertise in at least two of the following: a. USB (2.0/3.0/3.1/3.2/4.0, USB-PD) b. Ethernet (100Base-TX, 1000Base-T, 10GBase-T, SGMII, XFI)

c. MIPI (D-PHY, C-PHY, CSI-2, DSI)Strong understanding of SerDes, PLL, CDR, equalization (FFE/DFE), and electrical compliance. Experience with Cadence/Virtuoso, Spectre, HSPICE, Verilog-A/MS, and related tools. Familiarity with lab measurement tools: oscilloscope, BERT, VNA, TDR, etc.

Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. Demonstrated ability to mentor junior engineers and lead by example.

Passion for innovation and the ability to challenge the status quo. Track record of patents, publications, or recognized innovation in the PHY or high-speed I/O domain.

Preferred Qualifications:Experience with multi-protocol PHY design. Participation in standards bodies (e.g., USB-IF, IEEE, MIPI Alliance). Experience with chip-package-board co-design.

Background in post-silicon validation and test automationQualifiers for the Role / Necessary Experience and Skills Required for the Role:Bachelor's/Masters/PhD degree in engineering in Electronics and Electrical Engineering with excellent academic records.

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