Memory Modeling Engineer

General Summary:

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Responsibilities/job duties

• Memory Frontend Model development/verification/delivery/debug/Automation

Memory Front End team introduction:

At Qualcomm memory team, we specialize in front-end modeling for a wide range of memory IPs. This includes various architectures such as single-port memories, pseudo dual-port designs, register files, CPU memories, and complex custom memories developed from the ground up. Each IP development undergoes comprehensive verificationcovering functional, formal, BIRA, and DFT domainsand is rigorously validated through an extensive QA suite to ensure alignment with the actual memory circuit implementation

Qualifications

Masters in Electronics and communication Engineering or Electrical Engineering or related field with 0-2 years experience.

In this position candidate will be part of memory FrontEnd modelling team where he/she will be responsible for below:

Design and implement behavioral modelsin Verilog/System Verilog for compiler-generated and custom memory components. Maintain and enhance memory compilersto ensure accurate generation of behavioral Verilog models. Develop and support LVLIB and MASIS modelsfor memory BIST (Built-In Self-Test) applications. Create FPGA-compatible modelstailored for emulation platforms. Build DFT (Design-for-Test) and Fast Scan modelsto support comprehensive test coverage.

Execute signoff simulationsfor both functional and formal verification across all compiler and custom memory models. Run comprehensive QA suitesto validate that all memory models accurately reflect the intended circuit implementations. Develop and maintain signoff verification tools and QA automation frameworksfor memory model validation. Conduct post-release QA checksto ensure model quality and reliability. Manage customer releases, ensuring readiness and documentation. Provide support to SoC teams, assisting with debugging and resolving memory interface issues related to the models.

In this position, candidates should have below understating and hands on experience:

Strong understanding of memory architecture and functionality. Solid grasp of CMOS low-power circuit design principles. Proficient in simulation tools such as Vsim, VCS, Finesim, and CustomSim. Deep expertise in Verilog and System Verilog coding practices. Familiarity with BIST modeling frameworks like LVLIB and MASIS. Good working knowledge of CLP and Static Timing Analysis (STA). Experience with Unix, Shell scripting, Perl, and Python is a plus. Excellent communication and collaboration skills.