CPU Integration CAD Engineer

2 weeks ago

Bengaluru, Karnataka, India Qualcomm Full time ₹ 12,00,000 - ₹ 36,00,000 per year

General Summary:

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

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Minimum Qualifications:

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

As CPU IntegrationCADengineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores. You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area.

Experience: 6 to 15 years of experience with good academics.

Roles andResponsibilities

  • Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD
  • Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis
  • Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts
  • Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area
  • Maintain and support implementation flows, and resolve project-specific issues
  • Work with EDA vendors to define roadmap and to resolve tool issues

Preferred Qualifications:

  • Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science
  • 10+ years of hands-on experience in development of high-performance chips - either in a design or CAD role
  • High level of programming proficiency (Python and TCL).
  • Knowledge of data structures and algorithms
  • Experience with automation
  • Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV
  • Experience with advanced technology nodes (5nm or lower)
  • Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre
  • Strong user of industry-standard place-and-route tools such as Cadence Innovus
  • Proven track record of managing and regressing place-and-route flows

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