ASIC Design Engineer

Amazon Devices is an inventive research and development company that designs and develops high-profile devices like the Kindle family of products, Fire Tablets, Alexa, Fire TV, Health Wellness, Amazon Echo & Astro products. This is an exciting opportunity to join Amazon in developing its next generation SOC's for the machine learning enabled consumer products. We are looking for exceptional engineers and engineering leaders to join our SOC development team and help develop the next generation of chips based on a revolutionary architecture. The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Integration Design Engineer to continue to innovate on behalf of our customers.
Work hard. Have Fun. Make history.

Key job responsibilities
In this role, you work in a team developing SoCs to be deployed in a range of Amazon devices. You will integrate industry standard and custom hardware IP and subsystems into SoCs to accelerate applications in machine learning, computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and physical design teams to develop SoCs that meets the power, performance and area goals for Amazon devices. You will help define the processes, methods and tools for design and implementation of large complex SoCs. Develop chip level and subsystem level netlists integrating IPs and new design.

• Work with Chip Architects to understand architecture and high-level product requirements.

• Convert Chip Spec into RTL using internal IPs and external IPs.

• Review Architecture and Design of custom IPs for integration into SOC's.

• Design & Develop RTL for Interfaces, Power Management, Clocking, Reset, Test & Debug.

• Develop and implement methodologies for I/O, DFT, Debug, Clocking and Power Management.

• Provide technical leadership through lead by example, mentorship and strong team work.

Basic Qualifications:

• BS degree or higher in EE or CE or CS

• 5+ years or more of practical semiconductor design experience including full-chip and subsystem RTL integration.

• Experience in micro-architecture definition from architecture guideline and model analysis.

• Experience in RTL coding (Verilog/System Verilog) and debug, as well as performance/power/area analysis and trade-offs

• Experience in closing full-chip and subsystem timing working with synthesis and static timing analysis teams.

• Experience with DFT tools for scan and BIST insertion

• Excellent verbal and written communication skills, collaboration and teamwork skills as well as ability to contribute to diverse and inclusive teams.

Preferred Qualifications:

• MS or PhD degree in Computer Engineering/Electrical Engineering or related field.

• Design experience in Datapath, flow control, Arbitration, FIFO, DMA , IOMMU, SOC bus architectures, Arteris NOC interconnect, ARM's AXI/AHB bus architecture & Protocols, Serial interfaces such as PCIe, QSPI, I2C,UART, EMMC, USB. LPDDR controller & Phy IP integration, embedded memory (SRAM, OTP etc;.) Other IP integration such as ADC, PLL, DLL, PVT sensors, GPIO & Debug (Coresight).

• In-depth knowledge of in one or more areas such as CPU, DSP, or programmable accelerators.

• SOC bring-up and post silicon validation experience

• Experience with early RTL power analysis.

• Experience with gate level testing and multi clock design practices.

• Successful tape outs of complex, high-volume SoCs in advanced design nodes

• Experience working closely with physical design teams to develop highly optimized ASICs with excellent power, performance and area.

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