Full Chip

6 days ago


Bengaluru, India ViteStork Consulting Full time

:
- Proven experience in top level floorplanning/block partitioning
- Power planning, understanding and planning of clock mesh structure/conventional CTS, Block integration (Including analog IP integration) and Physical Verification Signoff.
- Engineer should have experience in handling chips of GHz clock frequency range & multi-million instance, and designed complex chips in lower technology nodes (16nm and below).
- Padframe/BGA planning/design, including RDL routing is required.**Skills**
-:
**Physical Design, floorplanning**

**Job Location**
-:
- Bangalore**Experience**
-:
- 5 - 16 Years**Company Name**
-:
- Semiconductor R&D and Services- :**Contact Mobile**
-:
- N/A


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