
Pd Full Chip
3 days ago
**Responsibilities**:
SoC Floorplan Development: Develop chip floorplan with optimized padring integration for successful physical implementation.
Physical Synthesis and Optimization: Perform RTL synthesis and optimize designs for area, power, and performance.
Clock Tree Synthesis (CTS): Design and implement robust clock distribution networks, ensuring clock skew/jitter minimization.
Power Planning and Distribution: Plan and implement power distribution networks (PDN), power gating, and partitioning for low-power designs.
Place & Route (P&R): Execute the placement and routing of the design, including custom placement and routing tasks.
Timing Closure: Work on timing analysis and ensure timing closure across all process corners and operating conditions.
Signal Integrity Signoff: Conduct thorough analysis to ensure signal integrity (SI) and minimize crosstalk.
Physical Verification: Perform Design Rule Check (DRC), Layout Versus Schematic (LVS) verification, and power integrity analysis to ensure compliance with foundry rules.
Power Integrity Signoff: Execute IR Drop analysis, electro-migration (EM) checks, and power integrity validation.
DFM: Conduct Design for Manufacturability (DFM) checks to ensure high yields and compliance with manufacturing processes.
Fab Interaction for Tapeout: Collaborate with foundry teams to ensure a seamless tapeout process, handling all the necessary checks and interactions.
**Experience and Skills Required**:
Experience: 5-15 years of hands-on experience in SoC physical design and full-chip integration, covering the entire RTL-to-GDSII flow.
Expertise in Synthesis: Strong knowledge in logic synthesis, floorplanning, auto place-and-route (APR), and building/re-ordering scan chains.
Custom Layout and CTS: Expertise in custom layout design, clock tree synthesis (CTS), and parasitic extraction.
Pre/Post-Layout Timing Analysis: Solid experience in pre
- and post-layout static timing analysis (STA) for timing closure.
Physical Verification: Proficient in LVS and DRC, with a deep understanding of design rule checks and layout-vs-schematic validation.
Low Power Design: Extensive knowledge in low-power design techniques, including clock gating, power gating, and partitioning.
Power Integrity and DFM: In-depth understanding of IR drop, electromigration (EM), design for manufacturability (DFM), and power integrity.
Foundry Interaction: Strong experience working with foundry collateral and leading the tapeout process, ensuring all necessary checks and signoffs are completed with the fab.
**Job Category**:Others**Job Type**:Full Time**Job Location**:Bangalore**Experience**:5-15+ Years**Notice period**:0-30 days
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