Full chip PD

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. Full Chip Clock Architecture & Design Engineer THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Clocking team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have 10-15 years of minimum experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Full Chip Clock Architecture analysis, Design, and Implementation. Making use of ICC/FC physical design knowledge and exposure. Scripting in TCL/Python or other similar languages. Debug/decode existing scripts. Well versed with Constraints, STA and good knowledge of Primetime (PT). Circuit Simulations in Spice or inhouse tools. Circuit design support as and when required. Exposure to cell design is added plus. PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design or equivalent tools. Expertise on tool expected. Expertise in Full Chip Clocking or Sub-system level implementation. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience in Circuit Simulations/Design is a good advantage. ACADEMIC CREDENTIALS: Bachelors or Master's degree in Computer/Electronics/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.Full Chip Clock Architecture & Design Engineer THE ROLE: As a member of the Strategic Silicon Solution Group Full Chip Clocking team, you will help bring to life cutting-edge designs. You will work closely with the Full Chip/Subsystem Floorplan / Netlist, Tile/Block/Partition level Physical Design, Full Chip Static Timing Analysis and Constraints teams, to achieve first pass silicon success. THE PERSON: A successful candidate should have 10-15 years of minimum experience. He will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Full Chip Clock Architecture analysis, Design, and Implementation. Making use of ICC/FC physical design knowledge and exposure. Scripting in TCL/Python or other similar languages. Debug/decode existing scripts. Well versed with Constraints, STA and good knowledge of Primetime (PT). Circuit Simulations in Spice or inhouse tools. Circuit design support as and when required. Exposure to cell design is added plus. PREFERRED EXPERIENCE: Understanding of ICC2 or Fusion Compiler Physical Design or equivalent tools. Expertise on tool expected. Expertise in Full Chip Clocking or Sub-system level implementation. Experience in TCL/Python and other languages needed. Should be strong in scripting and decode/debug old existing scripts. Experience in Circuit Simulations/Design is a good advantage. ACADEMIC CREDENTIALS: Bachelors or Master's degree in Computer/Electronics/Electrical Engineering #LI-SR4Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.