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SOC Integration
3 weeks ago
**Skillset**:
RTL SOC Integration Design with Spyglass Lint CDC
Job Profile - RTL Micro-architecture Design Engineer (SOC Integration) 5+ years of work experience in VLSI RTL IP or Subsystem design. Based on prior skill and desire to learn, the new hire will contribute in either SoC Clock, SoC Power IP/Subsystem, BUS/Subsystem, Peripheral/CPU/GPU Subsystem or other Mobile SoC Subsystem. **Understanding of Digital design principles. AMBA SoC BUS protocols specifically APB, AXI and AHB.**
- Creating micro-architecture and detailed design documents for SoC Subsystem design keeping in mind performance, power, area requirements. **Strong debugging skills and very good experience in DV tools like Verdi, NCSIM. ** SOC Integration experience preferred of Top Level, Block Level or Subsystem level. **Working with DV team to enable verification coverage improvement. Working on GLS closure with DV, PD and Modelling team. ** Must have knowledge in clock domain crossing (CDC), Linting, UPF, DFT and Multi-Voltage-Rule-Check analysis. **Understanding on ASIC Synthesis, and static timing reports analysis, Formal checking, etc. is a must. ** Understanding and defining constraints and critical high speed path timing closure working with back end teams.
**Job Types**: Permanent, Full-time
**Salary**: Up to ₹2,500,000.00 per year
Ability to commute/relocate:
- Bengaluru, Karnataka: Reliably commute or planning to relocate before starting work (required)
Application Question(s):
- Are you comfortable with the Annual CTC upto 25 LPA?
- Are you an immediate joiner or Notice Period upto 30 days/1month ?
- Do you have minimum 5 years of work experience in VLSI RTL IP or Subsystem design?
