Ckt Design Fxte/subcon

**No**

**Skill**

**Mode of Hire**

**JD**

**Location**

**No. of Positions**

**1**

**Design Verification**

**FXTE/Subcon**

Bgl/Hyd/Noida

10

**Job Description**:

- You will be part of the team verifying IPs and SoCs leading to first Si success.
- IP verification is coverage driven using latest industry standard methodologies and HVLs.
- Work involves defining verification strategy, writing test plans, developing efficient test benches and test cases.
- Code coverage, Functional coverage and assertions are desired.
- ARM based SoC verification experience is an added advantage.
- Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc. is a great plus.
- Multiple positions with emphasis on AMS and Power aware verification.
- Should have worked on GLS.

Primary Skills
- Verilog, SV, UVM/OVM, IP Verification, SoC Verification, scripting - Perl, Python, Shell, and Tcl.

Secondary Skills
- Test bench / model / VIP development, Functional coverage, GLS, LEC, Emulation, AMS, ARM, Protocols AHB/AXI/APB, Ethernet, USB, PCIe, I2C, SPI, CAN, Mipi CSI/DSI, LPDDR.

**2**

**DFT Engineer**

**FXTE/Subcon**

**Description**:
Bgl/Noida

5
- Will be responsible for Designing and Implementing DFT techniques
- Should hava a good understanding of Memory BIST/Scan /OnChip Compression/At-speed Scan/Test-clocking/Boundary Scan/Analog Testing/Pin-muxing/LogicBIST on complex SOCs to improve testability.
- Test Modes implementation and verification, scan insertion including on-chip compression.
- Implementing, integrating and verifying memory BIST and boundary scan.
- ATPG Test vector (Stuck-at/At-speed/Path delay/SDD/IDDQ/Bridging fault) generation with high test Coverage and simulations at gate level with timing (SDF).
- Basic understanding of complete SOC design and flow.
- Excellent in problem solving and analytical skills
- Excellent communication, team work and networking skills

**Primary Skills**
- Should Have Good understanding of Design and DFT Architecture
- Should have been part of Tapeout SoC
- Well Versed with ATPG Tools & MBIST Tools

**Secondary Skills**
- Team Player, Strong Business Acumen with understanding of organizational issues (conflict resolution between stakeholders)
- Familiarity with Desired Flexibility and adaptability with respect to project management

**3**

**Analog layout**

**FXTE/Subcon**

**Job Description**:
**Blore**

**5**
- Hands on experience in developing Analog Layout / IO layout design.
- Good exposure on FinFet layouts in lower nodes. Expertise in using the best and latest features of Cadence and Calibre DRC/LVS.
- Good exposure on ESD, LUP, antenna layout challenges and analysing/fixing EMIR issues.
- Capable of working independently and with team and getting work done.
- The ability to work & communicate effectively with global engineering teams.

3
- Able to handle Analog Layout Design, EDA Tools, DRC, LVS, Calibre, FinFet.

Secondary Skills
- Knowledge in Cadence, Virtuoso, Physical verification.

**4**

**Analog circuit design**

**FXTE/Subcon**

**Job Description**:
Blore

5
- High speed interface design (HBMIO, PCIe Gen2/3/4, DDR4/5/6, USB2/3): Transmitter, Receiver blocks.
- LVDS Tx, LVDS Rx, GPIOs, Voltage / current mode drivers, Receiver front end amplifier.
- Equalizers: FFE, DFE, CTLE.
- Clock & data recovery, Phase Interpolators, PLL, DLL, clock distribution, Oscillators.
- Data Converters : ADC ( SAR, Sigma delta, pipeline), DAC.
- PMIC: LDO, Bandgap, POR, Switching regulators, Voltage Monitor, (Opamps/Comparators).

Primary Skills
- PLL, DLL, High speed interface design (HBMIO, PCIe Gen2/3/4, DDR4/5/6, USB2/3): Transmitter, Receiver blocks.

Secondary Skills
- PMIC, LDO, Bandgap, POR, Switching regulators, Voltage Monitor, (Opamps/Comparators ).

**5**

**PD**

**FXTE/Subcon**

**Senior Manager - Physical Design**

**Bgl/Noida**

**5**

**Description**:
Manage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with front-end engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting.

**Desired Skills & Experience**:
Experience level 10 to 15 years.

Must possess 10+ years of hands on experience in handling block/chip level implementation from Netlist to GDS

Must possess hands on experience in timing closure and physical verification closure

Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz

Experience in handling lower tech nodes that include 40nm, 28nm or lesser nodes etc.

Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC