Pd Fxte/subcon

**Description**:
Manage and lead a team of physical design engineers. Job also entails significant amount of hands-on work, in particular place-and-route, static timing analysis, formal verification, physical verification, and power analysis. Drive implementation of physical design methodologies as required through the development of automation scripts. Work with front-end engineers to resolve timing and power issues. Evaluate new tools, and creatively drive power reduction of designs. Must be proficient and highly capable in floorplanning and time budgeting.

**Desired Skills & Experience**:
Experience level 10 to 15 years.

Must possess 10+ years of hands on experience in handling block/chip level implementation from Netlist to GDS

Must possess hands on experience in timing closure and physical verification closure

Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz

Experience in handling lower tech nodes that include 40nm, 28nm or lesser nodes etc.

Must have hands on tapeout experience in lower tech nodes in any of the tools mentioned such ICC or SOC Encounter or mentor tools.

Must have the ability to think on the spot for quick solutions and work-around at the time of tape out to hit the schedule on time

Must possess excellent scripting skills - TCL or Perl

Experience in Synthesis and Formal is a plus

Excellent verbal and written communication skills are required.

Must possess excellent debug skills, analytical skills and the ability to work independently.

Must be highly motivated and possess excellent team spirit

Primary Skills:
Ability to lead a team size of minimum of 10 members who can handle Subsystem PNR activities, Subsystem timing closure and Subsystem physical verification

Secondary Skills:
Knowledge in Subsystem Synthesis, Subsystem IR drop, Subsystem Lec, Subsystem CLP