UST | RTL Synthesis | hyderabad

2 weeks ago


hyderabad, India UST Full time

Hi All,

JD:-


· Engineering Graduates with MS/MTech/ME (EE/CS/EC) with 5 years or BTech/BS/BE(EE/CS/EC) with 7years in VLSI industry

· Hands on experience with RTL Synthesis, STA, Formal verification, and DFT are required; for DFT, expect at least minimum understanding of clocking and reset to scan logic

· Must have recent 2-3 years of experience using Synopsys DCNXT/FC/PT/PTPX/Formality and Cadence's LEC

· Good exposure to challenges involving in adv technology nodes like TSMC 7nm and Samsung 8nm

· Scripting skills in Shell/Tcl/Perl

· Able to review reports and log files and at least have some level of debugging capability

· Low power implementation involving multi-Voltage and practical knowledge on UPF will be a definite plus


Please share your resume to


Regards,

Jaya



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